1. Field of the Invention
The invention relates to a combination of programmable logic devices and delay lines.
2. Description of Related Art
There are two basic approaches to digital electronic circuit design, synchronous and asynchronous. The synchronous approach involves clocking registers and other elements once every fixed time period, whereas in the asynchronous approach there is either no clock or many clocks operating at different times. Synchronous circuits are reliable and easy to design, since the timing is always fixed, but some speed is sacrificed since the clock period must be set for the slowest component in the system. In the asynchronous approach, the user can apply successive signals to each component in the system with whatever minimum timing is specified for each respective component. For example, in a typical DRAM controller design, a signal is first applied to a multiplexer to select a row address to be applied to the DRAM. Once the row address stabilizes, the /RAS signal can be applied to the DRAM. A signal is then applied to the multiplexer to cause it to select the column address, and when that stabilizes, the /CAS signal is applied to the DRAM. At a certain period of time thereafter, the data output of the DRAM stabilizes and may be clocked into a data register. In a fully synchronous design, the entire DRAM read process may require several clock cycles to complete, whereas in an asynchronous design, control signals can be applied to the respective components with much tighter timing, thereby improving effective DRAM access speed markedly.
Precision timing control is often achieved in asynchronous designs by using a tapped delay line to generate arbitrarily spaced timing signals. A delay line is an electrical component which provides a predetermined time delay from signal input to signal output. Passive delay lines are usually constructed of simple LC networks with no active components, whereas as active delay lines include active drivers to improve reliability, square up the timing signal, and reduce signal attenuation. A tapped delay line is a delay line which has several taps, each providing a signal at successively increasing time periods from the time that the signal is initially applied to the delay line input. Examples of tapped delay lines are the DS100, DS1005, DS1007 and DS1010 series of silicon delay lines manufactured by Dallas Semiconductor.
One problem with prior-art delay lines is that they are typically fixed upon manufacture and not adjustable by the user. Users who require delays other than those available on standard parts therefore must either have custom delay lines manufactured or be satisfied with non-optimum delays. Dallas Semiconductor will set the delay times of its DS1007 according to a customer's specifications, but this setting must be done at the factory. The inability of users to change the delays in the field can slow design cycles and generate wasted devices if the user's needs change. Users also need to purchase a variety of different delay lines to cover all applications, which increases inventory and production costs. Devices are available which include a fixed tapped delay line, with a user-addressed multiplexer to select which delay tap is to be gated out. This method offers more flexibility, but is pin-intensive and still requires a large number of devices to obtain a plurality of different delayed signals. User-adjustable VCO-based analog delay generators also exist, but they are much more complicated and more costly than a string of delay elements.
Another problem with prior-art delay lines is that they must be coupled with external logic in order to create desired signals. External logic wastes board space, adds to an already large power requirement, and can easily cause undesirable skews. Skews are undesirable since the user, designing for worst-case speed parameters, usually must add a 20-30% margin on speed designations to accommodate skews.
Yet a third problem is that existing tapped delay lines are limited by either resolution or total delay. With fine resolution and a limited number of output pins, only a limited number of taps can be placed and the total delay will be small. On the other hand, if the total delay is long, then the resolution may be too coarse. Several delay line devices are therefore usually required if long delays with fine resolution are desired. Multiple delay lines can be costly, can add skew, can add to board space and power consumption problems, and may cause monotonicity problems.